Chiplet Summit: Sarcina Technology showcases latest innovations to slash advanced packaging costs
09 Feb 2024 — Sarcina Technology, a US-based Application Specific Advanced Packaging (ASAP) service company, rolled out its WIPO service at the Chiplet Summit in Santa Clara, US, February 6–8.
WIPO stands for wafer-in and product-out, and eliminates the exorbitant costs of maintaining a hardware team for packaging, testing and production.
“Last year was the first Chiplet Summit conference. The topic was hot then. The conference attracted a huge number of participants. But major IP companies, Electronic Design Automation companies and Application-specific integrated circuit service companies did not show up. This year, most of them showed up and had a booth to demonstrate their latest technologies and capabilities,” Larry Zu, CEO at Sarcina Technology, tells Packaging Insights.
“The conference offered several good tutorial sessions. The speakers were getting better and better. More and more decision-makers at the C-level participated. Basically, the conference has matured rapidly, and the attracted audience job responsibilities have become higher and higher.”
“This means companies, large and small, no longer think ‘Chiplet’ is just an academic concept that comes out once every two years. All decision-makers sitting at the C-level offices have realized that Chiplet is for real — it is there. They’d better capture the opportunity and get onto the train or be left much behind,” says Zu.
Sarcina production services reduce engineering overhead and speeds time-to-volume, says Zu.Meeting advanced pack design needs
Sarcina Technology was founded in 2011 as a semiconductor packaging and testing turnkey company in Palo Alto, California, with a design and supply chain management office in Taipei, Taiwan. It is led by industry veterans from companies such as AT&T Bell Labs, DEC, Intel and TSMC, says Zu.
“Sarcina provides leading companies with package design, power integrity, signal integrity and thermal simulation services. In addition, the company offers wafer probing and final test hardware design, test program development and one-stop turnkey service.”
Today, the package design for typical single-die wire-bond or flip-chip packages has become standard. But Zu asserts that the ecosystem is still not mature for some advanced package designs.
The following packages are some of the examples of advanced packages:
- 2.5 D silicon interposer package.
- 3 D package.
- Chiplet package.
- Photonic IC package.
- Automotive or space-grade package.
“Semiconductor wafer foundries have not opened their advanced packaging facilities and services to any companies worldwide. Today, they are only open to their large customers, internal customers and strategic partners,” says Zu.
Zu explains that small companies who want to purchase advanced technology-node wafers for their own 2.5 D or 3 D packaging will find it challenging to tape out their chips to the wafer foundries.
“As a result, most of the external package design companies are unable to obtain the package design rules, and the situation slowed down the wide acceptance of these advanced packaging technologies by our high-tech industry.”
“For chiplet packages, photonic IC packages and automotive or space-grade packages, today’s ecosystem has no problems to handle. There are multiple package substrate manufacturers and assembly houses to choose from,” says Zu.
He continues that Sarcina has been actively working with the OSAT (On-Site Assessment and Training) companies to encourage them to develop and offer their own advanced packaging technologies and solutions to any customers worldwide.
“Two weeks ago, Sarcina joined the Intel Foundry Services (IFS) Design Services Alliance program. Sarcina expressed its customers’ desire for IFS to open its 2.5 D and 3 D packaging services to external customers. Today, we only need one wafer foundry to open its advanced packaging facility to any external customers. Then all the rest of the wafer foundries will follow.”
By Natalie Schwertheim
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